[LowerSeqToSV] Move `RANDOM` calls into for statement

[uenoku]

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Input:

circuit Foo:
  module Foo:
    input clock: Clock
    input d: UInt<49>
    output q: UInt<49>

    reg _r: UInt<49>, clock
    _r <= d

    reg r: UInt<49>, clock
    r <= d

    reg s: UInt<49>, clock
    s <= d

    q <= s

current output:

      automatic logic [31:0] _RANDOM_0;
      automatic logic [31:0] _RANDOM_1;
      automatic logic [31:0] _RANDOM_2;
      automatic logic [31:0] _RANDOM_3;
      automatic logic [31:0] _RANDOM_4;
      `ifdef INIT_RANDOM_PROLOG_
        `INIT_RANDOM_PROLOG_
      `endif
      `ifdef RANDOMIZE_REG_INIT
        _RANDOM_0 = `RANDOM;
        _RANDOM_1 = `RANDOM;
        _RANDOM_2 = `RANDOM;
        _RANDOM_3 = `RANDOM;
        _RANDOM_4 = `RANDOM;

Ideally it can be expressed as

      automatic logic [31:0] _RANDOM [4:0];
      `ifdef INIT_RANDOM_PROLOG_
        `INIT_RANDOM_PROLOG_
      `endif
      `ifdef RANDOMIZE_REG_INIT
        for (i=0;i<4;i++)
        _RANDOM[i] = `RANDOM;
       ...