[ExportVerilog] Emit extra parentheses around reduction ops

[uenoku]

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This closes https://github.com/llvm/circt/issues/3001. This PR is a follow-up onto https://github.com/llvm/circt/pull/3015 which didn't consider cases where unary operators appear in the head of subexpression such as a & b & &a & a. This PR fixes the issue by directly inspecting outBuffer and finding a character used just before the current emission.

Example:

hw.module @Foo(%a: i4, %b: i1) -> (o1:i1) {
  %one4 = hw.constant -1 : i4

  %and1 = comb.icmp eq %a, %one4 : i4
  %and2 = comb.icmp eq %a, %one4 : i4
  %and3 = comb.icmp eq %a, %one4 : i4
  %and = comb.and %and1, %b, %and2, %and3  : i1
  hw.output %and : i1
}

circt-opt -export-verilog produces:

module Foo(     // bar.mlir:1:1
  input  [3:0] a,
  input        b,
  output       o1);

  assign o1 = &a & b & (&a) & (&a);     // bar.mlir:4:11, :5:11, :6:11, :7:10, :8:3
endmodule