lizajoseph

I would like to know if this design can be targeted on Alveo u50 xilinx_u50_gen3x16_xdma_5_202210_1 platform?

Error during creation of HLS IP cores

2

When I do “make all”, I seem to get the same error on HLS ip cores as seen below. WARNING: [Vivado 12-3523] Attempt to change 'Component_Name' from 'axis_256_to_64_converter' to 'axis_256to_64_converter'...

Can the XUP vitis network design work with 10G/25G Ethernet IP instead of the existing 100GEthernet IP ?

3

**For Vivado questions, please use [Vivado forum]( https://forums.xilinx.com/t5/Vivado-RTL-Development/ct-p/DESIGN)** **For Vitis questions, please use [the Vitis forum]( https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/bd-p/tools_v)** **For Vitis questions, please use [the Vitis forum]( https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/bd-p/alveo)** **For pynq questions, please...

How to simulate and test the verilog-ethernet design?

6

I would like to run and simulate the verilog-ethernet design. I have installed cocotb, cocotb-test, however I am not clear on how to run the tests for this design and...

How to download and install Icarus Verilog in linux environment?

1

I want to run the simulation tests for this design , however I am unable to run the test with the command "make WAVES=1". I get below error. FST warning:...

Is there any block diagram available for this design? Currently only module descriptions are available and it would be helpful to understand the design with a block diagram to understand...

Can this design be validated on Alveo u50 card ?

9

Hi, I came across your design as I am looking for a Ethernet design with UDP listener to be implemented on FPGA. I have a Alveo u50 card installed in...