lizajoseph

> After the latest commit to `ip_eth_tx_64.v` (`9b5a8cf24aeeeee9d0eadabb3136f7e7722544e2`), the MyHDL testbench hangs indefinitely:  > > The only changes I made were to tell the testbench where to find the...

> It looks like you need to install `scapy`, which is used for constructing and deconstructing network packets for testing. Thank you very much, I am able to run the...

I was able to download and install icarus verilog version 10.3 from below link https://sourceforge.net/projects/iverilog/files/iverilog/10.3/verilog-10.3.tar.gz/download

Does this design support 10G Ethernet IP targeted on Alveo u50? - I observe that the output from the 100G Ethernet IP CMAC kernel is 512 bit AXI4 stream whereas...

Okay, Thanks for your confirmation.

Yes, I have a programming cable that is attached to the u50 card. I can program the FPGA card using this programming cable. But could you let me know how...

I would like to test and validate the FPGA logic on the u50 card

I have programmed the bitfile on the Alveo u50 card via the u50 programming cable. Then I tried to set the IP address for my u50 card using this command...

Hi Alex, Thanks for sharing the Readme and the IP address details that is configured on the FPGA card. After programming the bitfile to the u50 card. I tried the...

Yes, you are right. I had built the fpga_AU50 which you pointed out that it is 25G version. Now I have built the fpga_AU50_10g folder design and programmed the bitfile...