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                                            leeguang517

The L2 cache of the VexiiRiscv CPU causes the BIOS to hang during startup on the ECP5 FPGA.

I tried instantiating the VexiiRiscv CPU on an OrangeCrab development board based on the ECP5 FPGA. Once the L2 cache is enabled, the BootROM reports a “BIOS CRC error” during...