The L2 cache of the VexiiRiscv CPU causes the BIOS to hang during startup on the ECP5 FPGA.

[leeguang517]

I tried instantiating the VexiiRiscv CPU on an OrangeCrab development board based on the ECP5 FPGA. Once the L2 cache is enabled, the BootROM reports a “BIOS CRC error” during startup, and then the system freezes at the DDR test stage, as shown below:

         __   _ __      _  __
        / /  (_) /____ | |/_/
       / /__/ / __/ -_)>  <
      /____/_/\__/\__/_/|_|
    Build your hardware, easily!
 
  (c) Copyright 2012-2025 Enjoy-Digital
  (c) Copyright 2007-2015 M-Labs
 
  BIOS built on Aug  9 2025 08:30:15
  BIOS CRC failed (expected 687589ef, got 13d46e92)
  The system will continue, but expect problems.
 
  LiteX git sha1: f98b288e9
 
 --=============== SoC ==================--
 CPU:            VexiiRiscv (rv64i2p0_mac) @ 48MHz
 BUS:            wishbone 32-bit @ 4GiB
 CSR:            32-bit data
 ROM:            64.0KiB
 SRAM:           8.0KiB
 FLASH:          16.0MiB
 SDRAM:          512.0MiB 16-bit @ 192MT/s (CL-6 CWL-5)
 MAIN-RAM:       512.0MiB
 
 --========== Initialization ============--
 
 Initializing SDRAM @0x40000000...
 Switching SDRAM to software control.
 Read leveling:
   m0, b00: |01110000| delays: 02+-01
   m0, b01: |00000000| delays: -
   m0, b02: |00000000| delays: -
   m0, b03: |00000000| delays: -
   best: m0, b00 delays: 02+-01
   m1, b00: |01110000| delays: 02+-01
   m1, b01: |00000000| delays: -
   m1, b02: |00000000| delays: -
   m1, b03: |00000000| delays: -
   best: m1, b00 delays: 02+-01
 Switching SDRAM to hardware control.
 Memtest at 0x40000000 (2.0MiB)...
   Write: 0x40000000-0x40000000 0B

The command-line parameters for building the LiteX SoC are:

 --cpu-type=vexiiriscv \
 --update-repo=no \
 --cpu-variant=linux \
 --vexii-args="--xlen=64 --with-rvc" \
 --l2-bytes=131072 \
 --l2-ways=8 \
 --with-coherent-dma \
 --integrated-rom-size=65536 \
 --build

After multiple attempts with different parameter combinations, I found that these two parameters are causing the issue:

 --l2-bytes=131072 \
 --l2-ways=8 \

This issue seems to be specific to the ECP5 FPGA — it does not occur when using Xilinx FPGAs or during Verilator simulation.