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kuznia-rdzeni
RISC-V out-of-order core for education and research purposes
There are two types of Method interfaces in our code: * Declaring Methods with `def_method` to be called by some external Transaction * Passing external Methods via Module constructor to...
CSR internal mechanism compliant with RISC-V privileged spec (`mip`, `mie`, etc.). Further work would include implementing (some of my finding on this mess): * ACLINT (CLINT is now deprecated). ACLINT...
Implement solution 3. from discussion on Speculation Backend: https://github.com/kuznia-rdzeni/coreblocks/pull/557#issuecomment-1894099078 Would make solution progress in #498 - but works only for waiting operations in FUs that use RS. Separate optimization would...
This PR is (Yet Another) experiment in making tests simpler to write. The testing mechanism introduced here runs settles when needed, so that a test writer never needs to write...
Currently we have two transactron-friendly implementation of FIFO: `BasicFifo` and `FIFO`. It is unlikely that we need two of them, so we can get rid of `FIFO`, as it doesn't...
Common bus master mock has been added in order to remove dependencies on specific bus implementation in unrelated tests.
Suppose we have a code like this: ```python @def_method(m, method1): def _(): method3(m) @def_method(m, method2): def _(): method3(m) with Transaction().body(m): with m.If(foo): method1(m) with m.Else(): method2(m) ``` Currently, an exception...
The task is to extend the multiplication support from #114 by a pipelined multiplier. The module should: * Be able to use the multiply-and-add capability of FPGA DSP elements (with...
The CSRs in question are: * [ ] `misa` * [x] `mvendorid` * [x] `marchid` * [x] `mimpid` * [x] `mhartid` * [ ] `mstatus` and `mstatush` * [x] `mtvec`...
To use whole potential of out-of-order execution we need a speculation over jumps. As for now we stall whole pipeline till branch is retired. Instead of that we should: -...
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RISC-V out-of-order core for education and research purposes