Implement compliant internal interrupt controller

[piotro888]

CSR internal mechanism compliant with RISC-V privileged spec (mip, mie, etc.).

Further work would include implementing (some of my finding on this mess):

• ACLINT (CLINT is now deprecated). ACLINT provides external memory mapped layer for mtimecmp - timer interrupts and IIRC for IPI (inter processor interrupts). ACLINT is backwards compatible with CLINT that (probably) is widely supported.
• SiFive CLIC looks like an alternative to ACLINT, that also partially replces internal CSR controller handler (but both modes must be supported). It is probably too complex and unnecessary for now. It is standarized by RISC-V now.
• Next layer of interrupt management (only external hardware interrupts) - PLIC also needs to be implemented to support Linux. Originally specified by SiFive, now standarized byt RISC-V too.

Some sources:

• https://www.starfivetech.com/uploads/sifive-interrupt-cookbook-v1p2.pdf
• https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc#interrupts
• linux-on-vexriscv