Krste Asanovic
Krste Asanovic
Extension should either be incompatible with hypervisor extension, or behavior specified when hypervisor extension present.
Behavior is not specified in a few places (e.g., mscratchcsw).
As described in #228
From John Hauser, email March 10, 2019: As currently defined, the CLIC has a single configuration byte, 'cliccfg', that determines the splitting of interrupt control settings into levels and priorities....
This is a placeholder for an option to be added post-initial ratification.
The N-extension is not currently on a path to ratification. Can rewrite CLIC spec to allow for, but not assume, the N-extension is available.
RISC-V will have byte-address-invariant policy for memory-mapped devices in a bi-endian system, but this needs to be written up.
There is great current interest in half-precision floating-point, either in IEEE FP16 or bfloat16 format. The vector spec already has encoding space for these typesl, but the scalar support for...
RVTSO is not ratified, but should explain how vector memory instructions would operate under TSO.