Krste Asanovic

This would be a backwards-incompatible change in the unprivileged architecture. There is a much bigger barrier for unprivileged versus for the privileged architecture - basically it should be a major...

Can you give a use case for this new feature (updating other CSRs without updating mstatus)?

Continuing discussion on the code size version of the issue. https://github.com/riscv/riscv-code-size-reduction/issues/134

TG Meeting 2022/4/12: The inconsistency of NOTE requiring FENCE.I #206 whereas the access was considered a data access was noted. Either this requirement should be dropped (meaning hardware has to...

Changed spec to match the Zce behavior - see #227.

Could use a non-normative comment to help explain table permissions settings for one or both of hardware and software vectoring.

The csip interrupt was meant for the background thread, and is allocated such as to have the lowest fixed priority (so an interrupt level does not need to be expended...

From TG meeting 2022/5/10: Agreed that it would be useful to set a breakpoint entry on table address, but might not be practical to implement in all systems depending on...

TG meeting 2022/7/19: To condense the previous comment: For implicit hardware table reads, whether breakpoints trap on the table read is left as an implementation option. For explicit loads used...

Hi Dmitri, The proposed instructions make sense and are close to what we had in an earlier version of the spec. They were dropped at some point, probably because they...