Krste Asanovic

I can't see this potential optimization justifying adding a whole another set of indexed store instructions. I see that in many cases, the ordered indexed store will only be consumed...

There should a later vector extension that covers more bit manipulation operations including shifts/rotates, so don't want to complicate base instructions as these operations will get subsumed. The example is...

The spec is designed to allow mixed-width code to work without knowing VLEN, and without tying up more architectural vector registers. A conventional implementation would not support the LMUL values...

The general intent is for future RVA profiles to retain backward compatibility with earlier profiles. Dropping an option does not break backward compatibility, as a portable binary must have used...

Closing as issue has been addressed.

"may not" not present in current text. It is probably time to add names for the different types of misaligned support.

The intent is to include Svadu in RVA23 as an option but disabled by default at launch of supervisor execution environment (i.e., your option 2).

It is concerning (or maybe reassuring?) that QEMU effectively had HADE=1 by default, but quite a few silicon systems shipped with HADE=0, and no one seemed to notice until recently....

I believe this has been addressed so closing.

The draft RVM23 profile was added to provided the first example of a standardized ISA across microcontrollers. The primary audience is toolchain and library developers, as well as MCU customers,...