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Published 20 hours ago • verified publisher icon riscv

terminology issue

Open mark-riscv opened this issue 2 years ago • 1 comments

in this section. a new phrase "may not be supported" is introduced. shouldn't it be unsupported optional?

==== RVI20U32 Mandatory Base

RV32I is the mandatory base ISA for RVI20U32, and is little-endian.

The ecall instruction causes a requested trap to the execution environment.

Misaligned loads and stores might not be supported.

The fence.tso instruction is mandatory.

mark-riscv avatar May 11 '22 15:05 mark-riscv

"may not" not present in current text.

It is probably time to add names for the different types of misaligned support.

kasanovic avatar Jun 01 '22 21:06 kasanovic