jameshegarty

Also @leonardt there was a breaking change to the combinational file on my machine which I fixed (?) here.

It seem like right now, if you have a signed add module, you can send unsigned inputs to it and it will wire it without an error. IMO I would...

That'd be cool, I'd be happy to help too once I clear my plate of some other stuff :)

Doc describing best practices: what is the right way to write generators, what is the wrong thing to use generators for. Differences between verilog generate statements & python metaprogramming.

I think this is just a regression b/c I don't test things on FPGA automatically (unfortunately), so the FPGA harness has gotten out of date. I will do that soon...

Let me know if this is blocking you in the short term.

What about the top level module, which may be driven by a global signal (like frame_start)? This would then need to be a module of type nil->Handshake(A). How else should...

It would at least be nice for MakeHandshake to put the valid bit in the valid bit slot in Systolic, so that when we lower to verilog it isn't packed...

The challenge with having a separate data/valid slot: now the "call" operator has to return two values, but we are not currently set up for that.

- Is there any reason for a module to have multiple resets? We should prob just change DFF to have a 'reset' fn. - If we use CE as ready,...