Add ready/valid to systolic

[jameshegarty]

issues:

• "if" statements (overriding valid bits when 'calling' other functions)
• Do we ever override the "CE" when 'calling' a function in the Rigel codebase? Why would you do this? (i.e. like how we can override the 'valid' bit)

One thing that is hard to understand about the behavior of the current system is the effect of the automatic CE/Valid wiring. If we 'call' a method on an instance from multiple 'functions', this call might get wired with different valid/CE in the multiple calls (which then means this turns into multiple real calls). We might not have even 'called' the method twice in our code - the same IR node may have just been used under multiple functions. When this happens, we get an error about a function being 'called' multiple times, but to the user this doesn't appear to be the case, and it's really hard to understand where the multiple calls come from. ** This is why functions should always be treated as the version of themselves with the least number of signals. Maybe you add signals if you need to (to connect stuff), but you should also be able to ignore them, if the function doesn't actually use them.

[jameshegarty]

It would at least be nice for MakeHandshake to put the valid bit in the valid bit slot in Systolic, so that when we lower to verilog it isn't packed in with the data.

[jameshegarty]

The challenge with having a separate data/valid slot: now the "call" operator has to return two values, but we are not currently set up for that.