Simplify Systolic

[jameshegarty]

• Add special case wiring for valid, ready, reset, uniforms (taps). Allow wiring of handshake directly (b/v valid, ready get wired automatically in systolic). See #13. Will this mean V->RV, HS basically get merged? is there any difference there?
• Remove call arbitration thing. Remove transaction thing. If you want to support this, you have to do onlyWire
• Add fixed point type as a built-in. See #8

[jameshegarty]

• Is there any reason for a module to have multiple resets? We should prob just change DFF to have a 'reset' fn.
• If we use CE as ready, we will now have to implement bidirectional wiring when we lower to Verilog! So we maybe don't want to attempt this.