Teguh Hofstee

I'm not necessarily advocating for this but https://github.com/PyHDI/Pyverilog and https://github.com/PyHDI/veriloggen exist. They don't support things I find useful like multidimensional arrays (all packed/unpacked dimensions need to be flattened to a...

`Source/SpireCore/SpirVCodeGen.cpp` is the relevant file. There are GLSL and HLSL code gen in that folder too that you could cross reference. The SpireMiniGameEngine repo has a Vulkan backend that will...

I'm not sure if I should put this here on in the other thread, but one case where an async active-low reset would be useful (even in FPGAs) is when...

If the AXI clock is the same as your system/reference clock then I don't see why you would?

For example, a Zynq exposes AXI ports as one of the main means of communicating between the processing system and the programmable logic. Those might actually be synchronous resets but...

Bumping this just to show there's still interest in this.

I tried my hand at making the original spinner by @zfedoran adhere more closely to the material design implementations. This is inspired by the implementation in Flutter ([found here](https://github.com/flutter/flutter/blob/1aedbb1835/packages/flutter/lib/src/material/progress_indicator.dart#L411)), and...

What if I wanted to make let's say 5 copies of a custom service? I could use `BUILDKITE_AGENT_SPAWN` but then they all have the same name and can't run at...

I've seen lots of inverters get added to a design since tools will often synthesize things to use active-low resets (sometimes due to what's available in technology libraries). That ends...

> For ASIC one typically does tech mapping on the full flattened design, this allows yosys optimization pass to remove all double inverters. We were using Design Compiler and Innovus,...