Shou-Li Hsu comments

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                                            Shou-Li Hsu

Verible formatter: Formatted output is lexically different from the input (Mismatched token enums.)

Got the same error. Reproduce with the following code: ```systemverilog `define LOG2(x) $clog2(x) module foo; logic [`LOG2(4):0] bar; endmodule ```

Error message is printed when formatting assertion with $fatal

Same issue here. Based on IEEE Standard for SystemVerilog (IEEE Std 1800-2017), some system tasks like `$finish`, `$fatal` allow users not to add the parenthesis pair behind. Currently, `$stop`, `$finish`,...

There is no syntax highlighting in VS Code

I have a repo dedicated to highlighting SystemVerilog syntax in VS Code, which is still under development. However, it is sufficient for most use cases: https://github.com/hankhsu1996/vscode-better-systemverilog-syntax. This might be useful...

Support for Comment-Based Warning Control

I prefer not to use comments for controlling tool behavior either. However, if we're considering simpler one-line diagnostic controls in the future (something like `logic my_var; // -Wno-unassigned-variable`), comments might...

Warnings to capture binary operations width mismatch

@jrudess, I have tried `-Wextra`. Since it only checks for width mismatches in assignments, we cannot always rely on it to capture mismatches in RHS. For example, in the code...