There is no syntax highlighting in VS Code

[DeflateAwning]

A couple of questions first

• Your IDE/editor (e.g. vscode, emacs,...) you use with verible LSP: VS Code
• IDE version: Latest
• What other SystemVerilog plugins are active alongside: None

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What activity failed When I open a SystemVerilog file, there is no highlighting/coloring.

Expectation I was hoping Verible would be my one-stop plugin for Verilog/SystemVerilog development, including syntax highlighting.

What actually happened There is no highlighting.

Note: it's possible that this is actually a feature request and not a bug report; please advise!

[hankhsu1996]

I have a repo dedicated to highlighting SystemVerilog syntax in VS Code, which is still under development. However, it is sufficient for most use cases: https://github.com/hankhsu1996/vscode-better-systemverilog-syntax. This might be useful for the project. However, combining static syntax highlighting with semantic analysis yields the best results. I'm wondering if there are any plans for Verible to implement semantic highlighting?