Paul Rigge

#157 was a result of the input/output relationship of operations being unclear. We should document carefully the width relationships in our typeclasses.

Everything should be on maven now!

Brought up with issue PR #102

Add new ExecutionOptions, Logging

13

[This code in DspTester](https://github.com/ucb-bar/dsptools/blob/master/src/main/scala/dsptools/DspTester.scala#L93) prints messages every time. Ideally, dsptools would use the same logging infrastructure as everything else. @stevobailey has an issue where DspPoke messages (among other things) fills...

Using DspReal somewhere should generate warning in verilog

1

We've talked about adding UInt -> DspReal functionality. We already have DspReal -> UInt. Having both makes it a lot easier for unsynthesizable code to get left in accidentally, especially...

Proc state elements of array type can be a scheduling barrier- even if each individual array element has a short backedge, the entire array can have a long backedge that...

We've talked about it a bunch in other issues, but I don't see a dedicated multi-proc codegen issue. I'll open this one an we can fill it in more when...

## Problem Statement Here are a few different issues that are all interrelated. PrioritySelect codegen should be specialized when `selector!=0`, in which case we want codegen to specify output as...

Cannot map parametric function

4

Mapping a parametric function doesn't work, e.g. ``` fn f(x: u32) -> u32 { N + x } fn main() { map(u32[4]:[0, 1, 2, 3], f) } ```

Currently, priority selects do not codegen for arrays. I have a fix incoming, but the fix has an issue: priority selects on different array types with the same element type...