Paul Rigge

Results 42 comments of Paul Rigge

Is this still an issue? I.e., if I'm getting `what(): could not open...` when testing #1230 it isn't something I'm doing wrong?

Some use cases: 1) You have a unit test that you want to run post-synthesis 2) You have a unit that interacts with the outside world in some way (e.g....

I have switched to doing bundle and vector expressions. So far it seems to work fine for literals and nesting these expressions. I'm currently not testing mixed direction bundle expressions....

Still failing, is there some stage/phase stuff I should be aware of?

I haven't tried it with a huge circuit, although I don't think it does anything most other passes don't already do a bunch of times. In the first pass, it...

@YingkunZhou it is definitely fair to say that _T_11 shouldn't be there, regardless of how it impacts final QoR. Is there firrtl output you can also post? It should be...

My output is ``` module Adder( // @[:[email protected]] input clock, // @[:[email protected]] input reset, // @[:[email protected]] input [7:0] io_in0, // @[:[email protected]] input [7:0] io_in1, // @[:[email protected]] output [7:0] io_out //...

You may not have installed firrtl- it's included as a dependency of chisel (see [here](https://github.com/ucb-bar/chisel-tutorial/blob/release/build.sbt#L42)). Perhaps forcing the latest 3.1.5 for chisel will fix things? The release is a little...

This looks to me like the pesky `-Xsource:2.11` issue. Scala 2.12 changed semantics for anonymous bundles (relied on structural types working in a more permissive way). In ammonite, the magic...

I'm not sure what's going on there as I am not a windows user. I think we generally advise windows users to use WSL- sometimes it is necessary to use...