Paul Rigge
Paul Rigge
One long-standing issue with the workflow with chisel-testers was that we always re-ran the chisel generator. Ideally, you'd be able to re-run all your unit tests on your top level...
Description says that a Named is a fixed point number and says what the binary point is. These will end up as comments in the emitted verilog. With this example:...
This is an attempt to add bundle literals to firrtl. I'll make an associated chisel PR.
Today @meheffernan and I talked about ways to optimize the critical path and number of stages. One capability that seemed useful was extracting a pipeline stage, running it through an...
In the current state, we only customize codegen for assert and gate ops. A future change I'm working on extends this functionality to most other ops, but it may be...
The documentation doesn't really touch on what is required of a root proc, and errors are sometimes mysterious. It makes sense that the root proc can't have recurrent state or...
Right now, `OneHotSel` and `OneHotSelect` (and others) are used in different places. We should make them consistent.
Right now, channels expect ready/data/valid, and data can only be a single port. Passes that rewrite channels (for example, to work with SRAMs) are an awkward fit for this- ideally,...
Right now, we have `test`, `test_proc`, `cfg`, and `quickcheck` "directives" which are similar to [rust attributes](https://doc.rust-lang.org/reference/attributes.html)[^1]. These directives result in different ast nodes being parsed, e.g. `#[test] fn some_test_function() {...