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Add description to fixed point numbers

Open grebe opened this issue 5 years ago • 6 comments

Description says that a Named is a fixed point number and says what the binary point is. These will end up as comments in the emitted verilog.

With this example:

circuit Example :
  module Example :
    input clk: Clock
    input a: Fixed<4><<2>>
    input b: Fixed<2><<1>>
    input c: Fixed<3><<0>>
    output out: Fixed

    reg sum: Fixed<5>, clk
    reg prod: Fixed<7>, clk

    sum <= add(a, b)
    prod <= mul(sum, c)
    out <= sub(prod, sum)

I get the following DescriptionAnnotations in the output annotations file (-foaf):

{
    "class":"firrtl.DescriptionAnnotation",
    "named":"~Example|Example>sum",
    "description":"Fixed point with binary point 2"
  },
  {
    "class":"firrtl.DescriptionAnnotation",
    "named":"~Example|Example>prod",
    "description":"Fixed point with binary point 2"
  },
  {
    "class":"firrtl.DescriptionAnnotation",
    "named":"~Example|Example>a",
    "description":"Fixed point with binary point 2"
  },
  {
    "class":"firrtl.DescriptionAnnotation",
    "named":"~Example|Example>b",
    "description":"Fixed point with binary point 1"
  },
  {
    "class":"firrtl.DescriptionAnnotation",
    "named":"~Example|Example>c",
    "description":"Fixed point with binary point 0"
  },

but I don't get any comments in the output verilog.

grebe avatar Feb 27 '19 01:02 grebe

Can you add a test of a FIRRTL design with fixedpoints in the unit tests, so we can see it failing to work?

azidar avatar Feb 27 '19 22:02 azidar

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CLAassistant avatar May 19 '19 23:05 CLAassistant

Still failing, is there some stage/phase stuff I should be aware of?

grebe avatar May 19 '19 23:05 grebe

@grebe are there potential performance regressions here, have you tried this with a circuit with a whole bunch of FixedPoints

chick avatar Jun 06 '19 18:06 chick

I haven't tried it with a huge circuit, although I don't think it does anything most other passes don't already do a bunch of times. In the first pass, it iterates through the whole circuit once and may potentially add a bunch of annotations. In the emitter phase, it goes through all the annotations and pulls out the descriptions. It adds more to the output verilog file too, but I think it's a worthwhile thing to do.

grebe avatar Jun 06 '19 19:06 grebe

Just curious. And I was more curious about any consequences downstream having more annotations to wade through. I think @seldridge did some analysis of this overhead so I wouldn't worry about it too much

chick avatar Jun 06 '19 20:06 chick