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PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

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## Expected Behavior Below is a good start - needs further update in the future. https://github.com/mabrains/globalfoundries-pdk-libs-gf180mcu_fd_pr/blob/main/models/ngspice/testing/README.md ## Actual Behavior https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/blob/main/models/ngspice/testing/README.md ## Specifications - Version: - Platform:

documentation

## Expected Behavior Below is a good start - still needs more details. https://github.com/mabrains/globalfoundries-pdk-libs-gf180mcu_fd_pr/blob/main/models/xyce/testing/README.md ## Actual Behavior https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/blob/main/models/xyce/testing/README.md ## Specifications - Version: - Platform:

documentation

In https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_09.html#lvs-bjt-mark-layer the layer is named `DRC_BJT` while it should be named `LVS_BJT`.

This page should be an index of design rules: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07.html The design rules are very difficult to find. They are only accessible through an expandable left menu like so: ![image](https://user-images.githubusercontent.com/12450095/213027700-dff73d20-9230-4658-8fcf-72f6679875c8.png)...

This section of the manual is missing information: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_04_2.html

## Expected Behavior The LEF files should be conforming to the fileformat specification ## Actual Behavior There are wrong commands in the LEF files: ![grafik](https://user-images.githubusercontent.com/6086693/205511093-4b286f67-9554-4c89-a3dd-ea186652bbb9.png)

## Expected Behavior On a page such as https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/SRAM/gf180mcu_fd_ip_sram/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/gf180mcu_fd_ip_sram__sram512x8m8wm1.html there is a box in the lower-right corner that says ` v: latest`. Clicking on this produces a window with options...

## Expected Behavior 1. The latch cells can be found in the PDK by Yosys+ABC. 2. The synthesis, floorplan, placement, and routing steps can be successfully completed by OpenLane with...

## Expected Behavior I want to discover the layout rules in human-readable form without knowing the rule numbers up front. ## Actual Behavior When I land on the readthedocs.io web...

@maliberty noticed that openrcx uses via resistances from the tech LEF. It does the same for layer resistances, even though that data is in the openrcx files. Longer term this...