Standard cell reference missing for DLATCH in gf180 PDK

[0616ygh]

Expected Behavior

1. The latch cells can be found in the PDK by Yosys+ABC.
2. The synthesis, floorplan, placement, and routing steps can be successfully completed by OpenLane with GF180 PDK.

Actual Behavior

1. ABC can't find latch cells in GF180 PDK and you can find cells named "$DLTACH_N" in synthesis report.
2. Floorplanning failed for module "$DLTACH_N" not found in "merged.nom.lef", and check whether EXTRA_LEFS is set appropriately.

Steps to Reproduce the Problem

1. git clone https://github.com/0616ygh/rioschip2.git
2. cd rioschip2
3. source env.sh
4. make setup
5. cd openlane
6. make green

Specifications

• OpenLane Version: OpenLane daae2154590cf20e0c20b77e3fc02b6526ad09af
• PDK Version: open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f
• Platform: Ubuntu 20.04