gf180mcu-pdk
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Standard cell reference missing for DLATCH in gf180 PDK
Expected Behavior
- The latch cells can be found in the PDK by Yosys+ABC.
- The synthesis, floorplan, placement, and routing steps can be successfully completed by OpenLane with GF180 PDK.
Actual Behavior
- ABC can't find latch cells in GF180 PDK and you can find cells named "$DLTACH_N" in synthesis report.
- Floorplanning failed for module "$DLTACH_N" not found in "merged.nom.lef", and check whether EXTRA_LEFS is set appropriately.
Steps to Reproduce the Problem
- git clone https://github.com/0616ygh/rioschip2.git
- cd rioschip2
- source env.sh
- make setup
- cd openlane
- make green
Specifications
- OpenLane Version: OpenLane daae2154590cf20e0c20b77e3fc02b6526ad09af
- PDK Version: open_pdks 0059588eebfc704681dc2368bd1d33d96281d10f
- Platform: Ubuntu 20.04