Ghada Dessouky

Does it work for N-block message?

5

It doesn't seem that this Verilog implementation works for messages of more than 1 block - is that so? And if it does work, how should the control signals be...

[hmac] Implementation of wider digest & configurable key length

1

This brings the implementation of the wider digest size and configurable key length for HMAC (issue #20968). This should allow the HMAC IP to compute SHA-2 and keyed HMAC using...

When I use a newer version of rocket-chip, "make rocket" does not successfully generate the Verilog. Testchipip cannot compile properly and generates many types not found errors. I try upgrading...

I am trying to recreate that RAM disk image from scratch but for another Linux kernel but I haven't been successful. How can I create and set it up from...

I'm trying to figure out the clock cycle latency for the L2 inclusive cache - for a hit/miss etc. I can't seem to find it documented anywhere. Can anyone help?...

Is there any documentation or block diagram available for the inclusive cache please?