blake2
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secworks
Does it work for N-block message?
It doesn't seem that this Verilog implementation works for messages of more than 1 block - is that so? And if it does work, how should the control signals be communicated to the core to manage digesting N-block messages?
I have tested the code via modelsim. There are some parameters u can only change from testbench. And you say N-block, 1 block input is 1024bits, and that's not enough ?
Isn't the next and final signals used to enable hashing multi-block messages? Does this core support hashing messages of size greater than 1024 bits, i.e., of more than 1 block?
Regards, Ghada Dessouky
On 11 July 2017 at 14:32, BoomAmplifier [email protected] wrote:
I have tested the code via modelsim. There are some parameters u can only change from testbench. And you say N-block, 1 block input is 1024bits, and that's not enough ?
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Hi, in my opinion: This verilog is only for 1024bits , the round matrix Sigma is 12 x 16.
And this code use lots of combinational logics to calculate Large-number operation （64bits XOR）. There are unacceptable time delay that the verilog's difficult to operate right on FPGAs.
Hope it's helpful.
Richie
It should work, but I need to investigate. 64 bit XOR is implemented in one layer of LUT/slices.
The core did not work as expected. I'm reworking the core from the bottom up. I've also added a reference model from the RFC to drive the testing.
I have updated the status for the core at the top of the README that it doen't work. I will change the status when I'm satisfied that the implementation works as it should. Including for multi block messages.