Ganesh Gore

Using canvas instead on SVG too render

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For bigger schematics (CRC.json) the rendering takes much longer. Do you believe using d3 canvas render instead of SVG will improve the performance?

The output for the following JSON code is different in the demo and locally compiled code. in the demo, the blocks are named `module2_1` and `module2_2` whereas in the local...

**Description** This pull adds github action to perform Open MPW precheck on github action on every push or pull request. The DRC results/checks are pushed in a separate branch named...

Added GSB documentation

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Adding documentation for general switch box XML files > ### Motivate of the pull request > - [ ] To address an existing issue. If so, please provide a link...

**Is your feature request related to a problem? Please describe.** This is based on recent PnR activities. During tillable architecture design, based on the selection of different wire segment ratio...

- Option to add remove successful task runs - Option to turn off logs - Run all tasks under the specific directory

**Is your feature request related to a problem? Please describe.** Due to the active and rapid development of this project, the XML syntax is constantly evolving. - Need to define...

**Is your feature request related to a problem? Please describe.** Currently the Verilog netlist generated uses net naming convention like `bottom_grid_pin__`, `bottom_grid_pin__`. With minor changes in the architecture file (...

Support little-endian convention for the verilog netlist

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**Is your feature request related to a problem? Please describe.** Currently OpenFPGA generated Verilog netlist used big-endian convention, which is not most conventional way. Extra care needs to be taken...

In case of multi-clock design. The `grid_io `module have same clock input duplicated on multiple input pins. It can it be combined on the top level and have only one...