Support little-endian convention for the verilog netlist

[ganeshgore]

Is your feature request related to a problem? Please describe. Currently OpenFPGA generated Verilog netlist used big-endian convention, which is not most conventional way. Extra care needs to be taken while interfacing the signal on the GPIOs.

Describe the solution you'd like Prefer little-endian convention for the netlist, atleast for the top level signals.

[tangxifan]

@ganeshgore Action item: I will create a branch for this feature. We will work on that branch