Make net indexing version control friendly

[ganeshgore]

Is your feature request related to a problem? Please describe. Currently the Verilog netlist generated uses net naming convention like bottom_grid_pin_<index>_, bottom_grid_pin_<index>_. With minor changes in the architecture file ( like addition of the extra global signal ) it changes the Verilog netlist significantly. This makes it difficult to track the version of generated source. With this limitation designer has to rely on full functional verification to validate the incremental changes.

Describe the solution you'd like

• Please make net Indexing system less dependent on other signals, like xxxxx_grid_pin_<index>_ can restart numbering from 0 on each side.
• Global signals can be skipped from the indexing count

Describe alternatives you've considered

• Not really an alternative but if it is suitable you can provide option to overwrite index from XML file

Additional context You can evaluate this by adding extra global input signal and checking number of changed lines in the generated netlist