Will Dietz

Previously: #7467. ```mlir firrtl.circuit "LayersProbe" { firrtl.layer @A bind {} firrtl.module @LayersProbe(out %o: !firrtl.bundle) { firrtl.layerblock @A { %0 = firrtl.ref.send %o : !firrtl.bundle } } } ``` `circt-opt --firrtl-lower-layers...

[FIRRTL] Inliner: Support for ops with regions.

1

inlineInstances/flattenInstances: * Walk entire body, not only top-level operations. Fixes missing instances and allows inlining them when conservatively legal. * Reject inlining instances under when/match. inlineInto/flattenInto: Walk entire body using...

[FIRRTL][LowerSignatures] Const is dropped, breaking IR

1

Input: ```firrtl FIRRTL version 4.0.0 circuit ConstFlip : extmodule Sink : input x : const UInt public module ConstFlip : output out : { x : const { flip y...

[FIRRTL] extmodule's supporting enablelayer?

1

FIRRTL spec only covers this for modules, and use on extmodule's in untested and unverified. The following parses and compiles fine: ```firrtl FIRRTL version 4.0.0 circuit EL: extmodule X enablelayer...

This input should be rejected (cc #7447): ```firrtl FIRRTL version 4.0.0 circuit EL: extmodule X enablelayer EL : public module EL enablelayer EL : inst e of X ```

This is just another example of the sort that was recently fixed (#7415), and probably the hashing should have some sort of values added to the hash that indicate the...

Emitted SV uses variable before declaration

1

Consider: ```mlir hw.module @hoist_reg(in %dummy : i32, in %dummy2 : i32, out out : i17) { %res_reg = sv.reg : !hw.inout sv.initial { %tmp = sv.reg init %dummy : !hw.inout...

Consider this input: ``` firrtl.circuit "MatchTest" { firrtl.module @MatchTest(in %i: !firrtl.enum) attributes {convention = #firrtl} { %c0_ui8 = firrtl.constant 0 : !firrtl.const.uint %0 = firrtl.enumcreate Some(%c0_ui8) : (!firrtl.const.uint) -> !firrtl.enum...

Consider: ``` firrtl.circuit "MatchInline" { firrtl.module @MatchInline(in %i: !firrtl.enum, out %o: !firrtl.uint) attributes {convention = #firrtl} { %c255_ui8 = firrtl.constant 255 : !firrtl.uint {name = "c_out"} %c0_ui8 = firrtl.constant 0...

Input: ``` FIRRTL version 4.0.0 circuit Foo: option Platform: FPGA ASIC module DefaultTarget: input clock: Clock module FPGATarget: input clock: Clock module ASICTarget: input clock: Clock public module Foo: input...