Aliaksei Chapyzhenka

>NUMBER

1

``` forth \ >NUMBER TESTS CREATE GN-BUF 0 C, : GN-STRING GN-BUF 1 ; : GN-CONSUMED GN-BUF CHAR+ 0 ; : GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING...

- [x] #4 `UM*` - [ ] #5 `S>D` or `FM/MOD`

The following code: ``` forth : GS1 S" SOURCE" 2DUP EVALUATE >R SWAP >R = R> R> = ; T{ GS1 -> }T ``` Yields the error: ``` forth Error:...

The following code: ``` forth VARIABLE SCANS : RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ; T{ 2 SCANS ! 345 RESCAN? -> 345 345 }T...

``` forth Error: in line: 359 T{ 7 S>D -3 FM/MOD -> -2 -3 }T expected [ 1, -2 ] to deeply equal [ -2, -3 ]. Error: in line:...

Looks like one of the cases failing: ``` forth T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; ->...

In the following test: ``` forth T{ : DOES1 DOES> @ 1 + ; -> }T T{ : DOES2 DOES> @ 2 + ; -> }T T{ CREATE CR1 ->...

RTL Schematic View

42

[](https://symbiflow.github.io/summer-of-code) # Brief explanation A good RTL schematic view is very useful.  # Detailed Explanation * View can be rendered from some internal representation of synthesis flow via...

[](https://symbiflow.github.io/summer-of-code) :construction: Work In Progress :construction: # Brief explanation Digital timing diagram rendering engine https://github.com/wavedrom/wavedrom # Detailed Explanation WaveDrom needs your help: * :ocean: Digital timing diagram rendering engine: https://github.com/wavedrom/wavedrom...

[](https://symbiflow.github.io/summer-of-code) :construction: Work In Progress :construction: # Brief explanation [Verilog](https://en.wikipedia.org/wiki/Verilog) / [SystemVerilog](https://en.wikipedia.org/wiki/SystemVerilog) is a major hardware description language used in FPGA and Chip design. Tree-Sitter is an incremental parsing system...