Aliaksei Chapyzhenka
Aliaksei Chapyzhenka
Set of proposed APIs similar to SystemVerilog: `sim.stop()` -- The `$stop` system task causes simulation to be suspended. `sim.finish()` -- The `$finish` system task causes the simulator to exit and...
In generated CPP wrapper, brake at compile time when on of the following is incorrect: * name * direction * width assertions?
* `lodash.template` returns `code` * that `code` can be published with NPM package * that `code` can be required by application * application calls `code` with parameters to produce CPP...
Generate CPP, filelists, etc. from DuH document: https://github.com/sifive/duh Related to #9
Do you plan to generate a wrapper for the arbitrary verilog module? I have started this pinlist reader library https://github.com/drom/verilog-pinlist It uses this Verilog parser https://github.com/tree-sitter/tree-sitter-verilog Will it be useful?
Could you use the original C version of N-API : https://nodejs.org/api/n-api.html Example: https://github.com/drom/node-iio/blob/master/src/iio.c
AI prompt support * https://github.com/marimo-team/codemirror-ai * https://github.com/val-town/codemirror-codeium * https://github.com/asadm/codemirror-copilot In-browser LLM with WebGPU https://webgpureport.org/ * https://github.com/mlc-ai/web-llm * https://github.com/mlc-ai/web-stable-diffusion/