Aliaksei Chapyzhenka

Qualifying symbol  ## Abutted Symbols ### Symbols with no logic connections  ### Two symbols with a single logic connection  ### Two symbols with multiple logic connections ...

Ability to select standard for the symbols.

1

Tool should support multiple schematic drawing standards. ### Preliminary list of standards: **MIL(ANSI)**: MIL-STD-806, ANSI/IEEE Std 91-1984, ANSI/IEEE Std 91a-1991 **IEC**: IEC 60617-12, EN 60617-12:1999 **DIN**: DIN 40700 **GOST**: [ГОСТ...

split string for assign statements

1

``` js { assign:[ ["g0", "^ b0 b1"], ["g1", "^ b1 b2"], ["g2", "^ b2 b3"], ["g3", "= b3"] ]} ``` has to be equivalent to this: ``` js {...

[observable](https://observablehq.com/@drom/datapath-or-control-logic) Some of RTL structures describe **control Logic** and some **DataPath** There is no direct way in Verilog or VHDL to express one or another. In ASIC or FPGA both...

The goal is to take [truth table](https://en.wikipedia.org/wiki/Truth_table) of the n-input Boolean [lookup table](https://en.wikipedia.org/wiki/Lookup_table) and render the most compact and readable schematic representation of it. The are several graphical symbols can...

http://www.pld.ttu.ee/~maksim/benchmarks/ http://www.cs.upc.edu/~jordicf/Research/gavina/BIB/files/rr_early_dac09.pdf

https://pdfs.semanticscholar.org/b1d8/079cfd07bd8ad22e0ff2cbef863e3742c0c7.pdf http://www.cerc.utexas.edu/~jaa/vlsi/

Symbols collection

3

https://commons.wikimedia.org/wiki/File:Logic-gate-index.png  https://commons.wikimedia.org/wiki/File:2-MUX_Aufbau2_DIN40900.svg  https://commons.wikimedia.org/wiki/File:3MUX-Primzahl-Aufbau3_DIN40900.svg  https://commons.wikimedia.org/wiki/File:3MUX-Primzahl-Aufbau2_DIN40900.svg  https://commons.wikimedia.org/wiki/File:2-MUX_Aufbau_DIN40900.svg 

Need for units (boxes) with multiple outputs. extracted from: #5