Support Concurrent read/write access

[dpretet]

This branch contains updates in memfy and dcache to support concurrent read/write access if no address collision can occur. The updates are the following:

• memfy: AXI_ORDERING parameter set to 1 generate another circuit to detect the r/w collisions. Look-up tables (LUT) for read and write channels are instantiated to track ongoing requests. AXI_ORDERING=0 follows the previous behaviour, read and write requests can't be issued in parallel. Outstanding read blocks write requests, and vice & versa.
• dcache pusher: cache write is slightly different, all write needing to update the blocks are packed into a FIFO, emptied once no new write request are issued by memfy. Before this update, read and write were fully parallel.
• cache blocks: architecture evolved, now having two fully independent port, once for read data path (fetcher), once for write data path (pusher). A port makes write passing before read. Before this update, port 1 was read-only, port 2 write-only.

The branch is not yet merged because two problems encountered during debug, that can't be identified clearly neither understood for the moment:

• wba-testsuite / core configuration: at some point, memfy generates a log indicating too many write completions have been issued by the dcache. True for both icarus and verilator
• apps/repl: the benchmark command issued a load_misaligned exception.

[dpretet]

merge_memfy_opt is a temp branch, merging all but new cache blocks, to debug the current problems, without success for the moment.

Pusher update, stacking write request to update the cache lower by 4% the performance. The dCache architecture needs to be better study/planned to avoid that and permit concurrent accesses

[dpretet]

Maybe linked to the AXI-Crossbar bug:

https://github.com/dpretet/axi-crossbar/issues/9