Mohamed Gaber

Need some help figuring out what's wrong with this marker database

6

I have two marker databases- one generated by KLayout (for another design) and provided by a colleague, and one that is manually converted from Magic using a script. The one...

Tips on speeding up build time?

3

On my Linux box, without `qtbindings`, KLayout takes 1h30m to build- This is the build invocation I'm using. Does anything immediately stand out as needing a fix..? ```sh CC=clang CXX=clang++\...

Add ability to generate special patterns unlikely to be generated by pseudo-RNG, such as: * Alternating 0s and 1s * Half-and-half * All 0s * Walking block of 1s ###...

Currently, we leave it up to `DispatchQueue` to decide how many threads are in use. This may not be efficient for high TV increments.

Title

Cells that are in `no_synth.cells` for OpenLane do not mention a reason for exclusion, creating confusion as to whether the cells themselves are bad or just cause issues with Yosys....

Many reference commits for `sky130` unknown

1

This appears to have originated with 7ddd413a3495a9055f03ae60b4320b14d0d6dc55: A lot of the reference strings volare depends on are set to "unknown":  Ideas?

Behavior difference between LEF/DEF DRC and GDSII DRC

10

In the following reproducible, the first variable is MAGIC_EXT_USE_GDS. When set to 1, DRC passes without a hitch. When set to 0, DRC fails: ``` user_project_wrapper ---------------------------------------- Metal2 spacing <...

Ignore undriven checks when running `SYNTH_ELABORATE_ONLY`

1

## Steps * `Yosys.*Synthesis` * Syntheses with `SYNTH_ELABORATE_ONLY` no longer report undriven nets as a check error (frequently for some top-level integrations, output pins are left undriven entirely to save...

Integrate LEF Parser

3

## Steps * `Verilator.Lint` * LEF views are now used as a fallback if no Verilog views are available for a Macro * New steps, `Misc.CheckMacroAntennaProperties` and `Misc.CheckDesignAntennaProperties` * Checks...