Mohamed Gaber
Mohamed Gaber
### Description Proposed by @ravenslofty from YosysHQ on Discord (thank you so much for the review!): ### Proposal * `abc` should be called with `-dff`, which attempts to optimize sequential...
### Description To maintain backwards compatibility with OpenLane 1, OpenLane 2 does not (by default) currently emit errors when there are hold violations in corners other than `*tt*`. ### Proposal...
### Description OpenLane is fairly deterministic on either macOS or Linux, i.e., the same inputs/design will broadly run into the same errors. However, a design failing on macOS may succeed...
### Description Some input netlists from non-Yosys tools may emit `assign` statements, which just tend to wreak havoc on some open-source tools (we think it's triggering a bug of some...
### Description According to @shalan: The naming of the vairable `SYNTH_ELABORATE_ONLY` may imply a process that is not what is actually being done. We need to investigate and change the...
### Description Investigation in https://github.com/The-OpenROAD-Project/OpenLane/issues/1697 shows that no-ops in Verilog, such as whitespace and comment, actually have an effect in Yosys. Per YosysHQ, this is a quasi-feature as it allows...
### Description OpenLane supports the use of deprecated variables in user-provided PDN and SDC files, however, it does not warn against their use within those files. ### Proposal _No response_
### Describe the bug Still toying around with `mpl2` when this happened  This VPWR strip doesn't have enough overlap to create a via and...
### Describe the bug Newer versions of OpenSTA require CUDD and links it as follows: ```cmake if (CUDD_LIB) message(STATUS "CUDD library: ${CUDD_LIB}") get_filename_component(CUDD_LIB_DIR "${CUDD_LIB}" PATH) get_filename_component(CUDD_LIB_PARENT1 "${CUDD_LIB_DIR}" PATH) find_file(CUDD_HEADER cudd.h...
~ `open_pdks` -> `c887119`