Integrate LEF Parser

[donn]

Steps

• Verilator.Lint

  • LEF views are now used as a fallback if no Verilog views are available for a Macro

• New steps, Misc.CheckMacroAntennaProperties and Misc.CheckDesignAntennaProperties

  • Checks the existence of antenna gate and antenna diffusion area on macro and final design pins respectively without invoking OpenROAD

• Yosys.*

  • LEF views are now used as a fallback if no Verilog views are available for a Macro

Misc.

• openlane.common
  • Toolbox
    • New method header_from_lef that creates a Verilog header from a LEF file

Tool Updates

• Added the Efabless ANTLR4-based lef_parser at v0.1.0

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Resolves #440

[openlane-bot]

Metric comparisons are in beta. Please report bugs under the issues tab.

To create this report yourself, grab the metrics artifact from the CI run, extract them, and invoke python3 -m openlane.common.metrics compare-main <path to directory>.

• No changes to critical metrics were detected in analyzed designs.

Full tables ► https://gist.github.com/openlane-bot/7a0a4f006c8db63c0cc30f0ab6211f09

[kareefardi]

Couple of initial comments:

• Can you add known limitations or language coverage or something similar to https://github.com/efabless/lef_parser?
• The bot is reporting a new result but I am not seeing any new designs added in the diff.

[donn]

This PR will not be merged until the LEF parser achieves more substantial coverage of the LEF standard.