David Koeplinger
David Koeplinger
E.g. ``` val d = DRAM[Int](1024) val x = SRAM[Int](32,32) x load d ``` Should generate an outer iteration over the rows of d, then a consumer which populates elements...
Noticed the new distinction between accel and host DRAM. While this is good, the way of creating these is not at all clear. At the moment, calling ```DRAM[Int](32)``` creates a...
``` val reg = Reg[Int](0) if (i.to[I32] == reg) 0x80.to[UInt8] else 0.to[UInt8] ``` Appears to be deleting the mux, but removing the `.to[I32]` fixes this. 
Include metadata for a set of constraints imposing the current control schedule (or, more generally, any requirements no the initiation interval). Add checks to routinely update the schedule after checking...
``` abstract class A extends Data[A](...) case object B extends A case object C extends A def setA(x: Sym[_], a: A): Unit = metadata.add(x, a) def readA(x: Sym[_]): Option[A] =...
``` val reg = Reg[Int] Reduce(reg)(0 by 1){i => ... }{ ... } ``` Case 1: The contents of `reg` after the loop is effectively unchanged. Is this the desired...
Using this issue to track all initiation interval calculation issues - [ ] #151 - Should depend on length between read and write, e.g. s(i) = f( s(i - 1)...
The following compiler changes should take effect when PIR gen is enabled: - [x] 1. Change switches to always be controllers (includes unit pipe insertion for conditions) [Priority 1] -...
@raghup17 @mattfel1 @kelayamatoz This repository now has significantly more lines of C or Verilog than it does Scala, which made me look into what is taking up all those lines,...
`Array.empty(size)` is currently the only way to create a mutable Array, but it isn't clear that the rest are immutable by default. Should make this clearer, not sure what syntax...