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Published 20 hours ago • verified publisher icon stanford-ppl

Updates for Plasticine

Open dkoeplin opened this issue 7 years ago • 6 comments

The following compiler changes should take effect when PIR gen is enabled:

  • [x] 1. Change switches to always be controllers (includes unit pipe insertion for conditions) [Priority 1]
  • [ ] 2. Change unrolled loops w/ enables to unrolled switches [Priority 1]
  • [ ] 3. Banking analysis on which access belong to which bank statically whenever possible. Place holder metadata banksOf [Priority 2]
  • [x] 4. Remove Parallel from IR [Priority 2]
  • [x] 5. Change LUT to SRAM (add metadata for initial value of SRAM and LUT) [Priority 2]
  • [x] 6. Disable buffer coalescing [Priority 2]
  • [x] 7. Transform Switch w/o effects or children and with return value to muxes [Priority 2]
  • [ ] 8. Change RegFile (no shift register) to SRAM (add metadata for initial value of SRAM and LUT) [Priority 3] Hold off for this
  • [x] 9. Add analysis to figure out which dimension of the sram is paralleled accessed across InnerController's inner most index. The resulting dimensions should be <= 1.

dkoeplin avatar Aug 29 '17 19:08 dkoeplin

I made some changes to the list with priority (smaller means more important). You can check off tasks when they are in develop. Thanks!

yaqiz01 avatar Aug 29 '17 20:08 yaqiz01

2 - Need to discuss with Matt - may change FPGA correctness 3 - Will be added with overhaul to banked accesses 7 - Requires representation of one-hot mux for Plasticine (or some other agreed upon thing)

dkoeplin avatar Sep 01 '17 20:09 dkoeplin

2 - Seems like it won't change correctness, but it sounds more expensive maybe. The plan is to get rid of the enables that come into controllers and instead wrap them inside switches?

mattfel1 avatar Sep 01 '17 22:09 mattfel1

Can 7 be converted to nested muxes? For example

If (c1) b1 else if (c2) b2 else b3 can be converted to Mux (c1, b1, mux(c2, b2, b3))

We can add one hot mux but ALUs have max 3 operands. so won't be albe to support selection more than two inputs

yaqiz01 avatar Sep 01 '17 22:09 yaqiz01

@mattfel1 yeah that's the general idea. Plasticine doesn't support enables on reads/writes/etc., so it always needs explicit enabling controllers around these things.

@yaqiz01 yeah you're right I think that should work.

dkoeplin avatar Sep 01 '17 23:09 dkoeplin

@dkoeplin For 1 is it possible to set Switch around the Switch Cases to have OuterControl ControlLevel? The only thing that's InnerControl level are the inner most switch cases

yaqiz01 avatar Sep 25 '17 19:09 yaqiz01