Mysterious mux deletion

[dkoeplin]

val reg = Reg[Int](0)
if (i.to[I32] == reg) 0x80.to[UInt8] else 0.to[UInt8]

Appears to be deleting the mux, but removing the .to[I32] fixes this.

[mattfel1]

I don't think this is the same root cause but I think its worth addressing and is kind of the same behavior. In SW_alg, we have if ((c == length | r == length) & ...) possible_entry_point := entry_tuple(r, c, update.score) c and r are iterators and length is an ArgIn. This code gets replaced with a hardcoded false, probably because it thinks an iterator will never equal an ArgIn and it is fixed if you do .value on the ArgIns. This seems like an easy thing to overlook and be confused about when debugging.

EDIT: I guess it shows warnings, but I think this is the kind of thing that should crash instead of warn