Dirk Hoffmann

More findings: - Opcode $60FF: In 68000 mode, opcode $60FF disassembles to ILLEGAL, because this bit bittern marks the BRA 32-bit-displacement instruction on the 68020+. On the 68000/68010, it should...

DIVU / DIVS: N flag is wrong

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Sorry to bother you again. This time, I have tested DIVU and DIVS and encountered an issue with the N flag. Test cases divu5: https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/DIV/divu5 This test case creates some...

Instruction: `suba.l D0, A0` Test case: sub1l https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/SUBA/suba1l Musashi: Amiga 500+ 🥰:  Conclusion: {m68k_op_suba_32_d , 0xf1f8, 0x91c0, { 6, 6, 2, 2}}, {m68k_op_suba_32_a , 0xf1f8, 0x91c8, { 6, 6,...

Instruction: `suba.w #$8000, A0` Test case: suba4 https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/SUBA/suba4 Musashi: Amiga 500+ 🥰:  Conclusion: {m68k_op_suba_16_i , 0xf1ff, 0x90fc, { 14, 12, 4, 4}}, must be: {m68k_op_suba_16_i , 0xf1ff, 0x90fc, {...

Instruction: `sub.l D0,D0` Test case: sub2 https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/SUB/sub2 Musashi (vAmiga): A real Amiga 500+ 🥰:  Conclusion: ``` {m68k_op_sub_32_er_d , 0xf1f8, 0x9080, { 6, 6, 2, 2}}, {m68k_op_sub_32_er_a , 0xf1f8, 0x9088,...

Instructions: `sub.b #$0, D0`, `sub.w #$0, D0` Test case: sub1 https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/SUB/sub1 Musashi (vAmiga): A real Amiga 500+ 🥰:  Conclusion: ``` {m68k_op_sub_8_er_i , 0xf1ff, 0x903c, { 10, 8, 4, 4}},...

Tested: `or.l D0, D0` Test case: https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/OR/or2 Musashi (vAmiga): A real Amiga 500+ 🥰:  Conclusion: Current: {m68k_op_and_32_er_d , 0xf1f8, 0xc080, { 6, 6, 2, 2}}, {m68k_op_or_32_er_d , 0xf1f8, 0x8080,...

Tested instruction: `or.b #$0, D0` https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/OR/or1 Musashi (vAmiga): A real Amiga 500+ 🥰:  Conclusion: ``` {m68k_op_or_8_er_i , 0xf1ff, 0x803c, { 10, 8, 4, 4}}, {m68k_op_and_8_er_i , 0xf1ff, 0xc03c, {...

ADDQ timing is wrong if destination is an address register

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Command `ADDQ.w ##, An` consumes 4 cycles in Musashi, but 8 cycles on a real machine. Line `{m68k_op_addq_16_a , 0xf1f8, 0x5048, { 4, 4, 2, 2}},` must be: `{m68k_op_addq_16_a ,...

The implementation of NBCD doesn’t seem to be correct. To verify this instruction, I’ve written four test cases: https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/NBCD #### nbcd1 Draws two 16 x 16 squares. In each square,...