AND.b / OR.b timing is off by 2 cycles in immediate addressing mode

[dirkwhoffmann]

Tested instruction: or.b #$0, D0

https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/OR/or1

Musashi (vAmiga):

A real Amiga 500+ 🥰:

Conclusion:

{m68k_op_or_8_er_i           , 0xf1ff, 0x803c, { 10,   8,   4,   4}},
{m68k_op_and_8_er_i          , 0xf1ff, 0xc03c, { 10,   8,   4,   4}},

must be:

{m68k_op_or_8_er_i           , 0xf1ff, 0x803c, { 8,   8,   4,   4}},
{m68k_op_and_8_er_i          , 0xf1ff, 0xc03c, { 8,   8,   4,   4}},