kstenerud
ADDQ timing is wrong if destination is an address register
Command ADDQ.w ##, An consumes 4 cycles in Musashi, but 8 cycles on a real machine.
Line
{m68k_op_addq_16_a , 0xf1f8, 0x5048, { 4, 4, 2, 2}},
must be:
{m68k_op_addq_16_a , 0xf1f8, 0x5048, { 8, 4, 2, 2}},
Instruction SUBQ is fine, only ADDQ is affected.
My test case is located here:
https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/ADDQ/addq1
The last line in the test picture visualises the timing properties of addq.w with an address register as destination:
Musashi (vAmiga):
A real Amiga 500+ 🥰:
Strange 🥴, back then in the old days I wanted my Cpu in the Amiga to delay as less as possible. I even recoded some portions of the kickstart to make it consume less cpu cycles without even knowing the meaning of the word hotspots 🙊🙄.
Now today we are a lot more sensible to the original behaviors of these precious old machines 🤓👍🏻
