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verilog testbench

2

 [axis_async_fifo_tb.txt](https://github.com/user-attachments/files/15907235/axis_async_fifo_tb.txt) [axis_async_fifo.txt](https://github.com/user-attachments/files/15907238/axis_async_fifo.txt)

Schematic viewer dosen't work

7

TerosHDL:Global output: 2024-06-19 09:53:02.780 [info] [00000.001204] ERROR: Can't guess frontend for input file `d:/workSpace/sim/fifo/axis_async_fifo.v;' (missing -f option)! When I'm in the CMD window input yowasp-yosys -p 'read_verilog axis_async_fifo.v;' , CMD...

axis_ll_bridge.v has some problems

1

Hi,Alex.I'm a little confused. In this code, the timing logic uses blocking assignments.