verilog testbench

[deleteTh]

axis_async_fifo_tb.txt axis_async_fifo.txt

[qarlosalberto]

Please, add more details.

[deleteTh]

When I use TerosHDL:Generate template >> Verilog testbench, then (wire wire) or (reg wire) will appear before some signal names. There will be grammatical errors.

[qarlosalberto]

Issue resolved. Please feel free to reopen the case if the problem persists.