deleteTh

[axis_async_fifo.txt](https://github.com/user-attachments/files/15896223/axis_async_fifo.txt) 

I found that many verilog file cannot be generated.


  [ErrorInfo.txt](https://github.com/user-attachments/files/15909257/ErrorInfo.txt)

When I use this command : yowasp-yosys -p 'read_verilog -sv d:/workSpace/sim/fifo/axis_async_fifo.v; ; hierarchy -top axis_async_fifo; proc; ; write_json C:/Users/LBWB_WT/.teroshdl_0hHab; stat', then CMD window was no error. 

always @(posedge clk) begin if (rst) begin last_tlast = 1'b1; end else begin if (s_axis_tvalid && s_axis_tready) last_tlast = s_axis_tlast; end end

When I use TerosHDL:Generate template >> Verilog testbench, then (wire wire) or (reg wire) will appear before some signal names. There will be grammatical errors.