darkriscv
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darklife
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
 I've got this FPGA board that I wish to support. It's got multiple buttons, LEDs, a camera port, and a vga port. There's also a small 7 segment display...
Comments, suggestions and discussions can be posted here: https://github.com/darklife/darkriscv/discussions For effective changes in the code (support for new boards, applications, etc), please open an issue first to discuss the topic...
Typical synthesis tools assume the defines as global, so a multi-core environment with non-symmetric configurations does not work... also, the defines may conflict with legacy defines already in use. By...
Although the DarkRISCV native data bus is very simple, flexible and faster (although not faster and flexible at the same time), the standard bus for FPGAs appears to be converging...
The big-endian support works only in the simulation. The problem is probably related to the gcc : even in the simulation the -Os optimization appears to not match with the...
I could not find any reference to somebody trying this on the Altera brand of FPGA. (I did not want to buy another kind of FGPA and download yet another...
Dear author(s), I tried to do a fresh compilation by removing all the .o and .s files from the src directory but no other changes. The compilation is successful but...
Hi all, I bought a board from Aliexpress and it looks like this . Is this board named khc40gbe_k420? Thanks a lot! https://github.com/darklife/darkriscv/tree/master/boards/aliexpress_hpc40gbe_k420
I advise adding a ISP function to darkriscv. At present, if I write some new C codes and generate new data for ram and rom, I have to use ISE...
1. I find that you use ```riscv32-unknown-elf-objcopy``` and ```hexdump``` to convert the ELF file to HEX file for simulation/FPGA BRAM initialization . I think you could have a look at...