Naoya Hatta

If Veryl can evaluate the bit width, the `logic` can be elided at transpile time. But if the evaluation will be done at compile time of SystemVerilog, it can't. For...

Standard interfaces like AXI, APB may be good candidates. This is because these interfaces will be used to connect between third-party libraries.

I created repository for standard library. https://github.com/veryl-lang/std The generated document is https://std.veryl-lang.org .

A primitive type evaluation is implemented at https://github.com/dalance/veryl/blob/master/crates/analyzer/src/handlers/check_enum.rs. It evaluates the size of enum members and checks whether the size is over the enum size. I implemented it as a...

The symbol table is used at some analyzer handlers and language server. For example, https://github.com/dalance/veryl/blob/9571195d062834f9c0b365e06344660c45c31191/crates/analyzer/src/handlers/check_function.rs#L39 https://github.com/dalance/veryl/blob/9571195d062834f9c0b365e06344660c45c31191/crates/analyzer/src/handlers/check_instance.rs#L45 > It looks like to use the symbol table in a separate pass, I...

Sorry for the late reply. I'ii check it by this weekend.

I'll close this issue because DAG implementation was already completed. Evaluation of type width will be done through #1017 .

I don't have an experience to write FF with async set and reset through `always_ff` declaration. Some people pointed out that such description causes mismatch between simulation and synthesis. https://stackoverflow.com/questions/18641159/can-systemverilog-represent-a-flip-flop-with-asynchronous-set-and-reset-without...

I think splitting file to for synthesis and simulation may increase file management cost. So using `ifndef SYNTHESIS` may be better than splitting file. ``` always_ff @(posedge i_clk or negedge...

I think that 3 or more reset semantics is clear. (Of course, I've never write such RTL in production...) ``` always_ff @(posedge i_clk or negedge i_set0 or negedge i_set1 or...