Naoya Hatta

Thank you for your suggestion. I've opened #65.

@Byron Sorry. I missed the problem of API design. The API of #65 doesn't have the way to specify default backticks count. In the current impl, it refers the hard-coded...

Alternatively the default value can be changed to 3. 3 is the minimum value allowed in spec. lf user want to use 4, the follow code is available. ```rust let...

This is a known restriction. ref: https://doc.veryl-lang.org/book/05_language_reference/14_generics.html > Additionally, the actual parameters should be accessible at the position of the generics declaration. For example, module names can be used as...

I'll close this issue because there is no way to handle the situation. If you have another idea, please reopen.

A syntax idea about generic `block` declaration. ```systemverilog block rggen_connect_bit_field_if:: { assign FIF.valid = RIF.valid; assign FIF.read_mask = RIF.read_mask[LSB+:WIDTH]; assign FIF.write_mask = RIF.write_mask[LSB+:WIDTH]; assign FIF.write_data = RIF.write_data[LSB+:WIDTH]; assign RIF.read_data[LSB+:WIDTH] =...

> It looks good. But why is instance name need? Is it to separate namespace? Yes. And adding name-less instantiation increases syntax and name-resolver complexity. The generated SV will become...

In your example, almost all syntax except keyword seems to be the same as instance declaration. And instantiation is not specialized for module, but also it is used for interface...

I think it is diffucult problem whether an invalid code should be rejected syntactically or semantically. In my experience of implementing a SystemVerilog parser (https://github.com/dalance/sv-parser), one of the most complicated...

Thanks. I misunderstood it like that you meant `const_expression` should be separated from `expression`. I agree that `ConstantExpression: Expression` is useful to ease semantic check.