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                                            Krishna Kumar

Fix issues with QLF_K6N10 cells_sim.v and dsp_sim.v

This PR has fixes for issues seen while simulating designs with the QLF_K6N10 device. The major changes are: - add specify blocks - add missing signals in dsp blocks to...

ql-qlf plugins: `-no_adder` flag affects cell parameters in output blif

From this section: https://github.com/chipsalliance/yosys-f4pga-plugins/blob/77fb7b17d96d9d5b1fcfb96711f4787cbf26bc4a/ql-qlf-plugin/synth_quicklogic.cc#L535 The logic is causing the cell parameters in output blif to not be written if `-no_adder` flag is passed in to `synth_quicklogic`. We are not sure...